/*******************************************************************************
 *                                    ZLG
 *                         ----------------------------
 *                         innovating embedded platform
 *
 * Copyright (c) 2001-present Guangzhou ZHIYUAN Electronics Co., Ltd.
 * All rights reserved.
 *
 * Contact information:
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 *******************************************************************************/
#ifndef __HC32F4A0_REGS_TIMER_H
#define __HC32F4A0_REGS_TIMER_H

#ifdef __cplusplus
extern "C" {
#endif  /* __cplusplus*/
#include "core/include/hc32f4a0_regs_base.h"
#include "common/hc32f4a0_common.h"

/* \brief HC32F4A0 定时器0 基本控制寄存器*/
#define TMR0_BCONR_HICPA_POS      (15U)
#define TMR0_BCONR_HICPA          (0x00008000UL)
#define TMR0_BCONR_HCLEA_POS      (14U)
#define TMR0_BCONR_HCLEA          (0x00004000UL)
#define TMR0_BCONR_HSTPA_POS      (13U)
#define TMR0_BCONR_HSTPA          (0x00002000UL)
#define TMR0_BCONR_HSTAA_POS      (12U)
#define TMR0_BCONR_HSTAA          (0x00001000UL)
#define TMR0_BCONR_ASYNCLKA_POS   (10U)
#define TMR0_BCONR_ASYNCLKA       (0x00000400UL)
#define TMR0_BCONR_SYNCLKA_POS    (9U)
#define TMR0_BCONR_SYNCLKA        (0x00000200UL)
#define TMR0_BCONR_SYNSA_POS      (8U)
#define TMR0_BCONR_SYNSA          (0x00000100UL)
#define TMR0_BCONR_CKDIVA_POS     (4U)
#define TMR0_BCONR_CKDIVA         (0x000000F0UL)
#define TMR0_BCONR_INTENA_POS     (2U)
#define TMR0_BCONR_INTENA         (0x00000004UL)
#define TMR0_BCONR_CAPMDA_POS     (1U)
#define TMR0_BCONR_CAPMDA         (0x00000002UL)
#define TMR0_BCONR_CSTA_POS       (0U)
#define TMR0_BCONR_CSTA           (0x00000001UL)

/* \brief HC32F4A0 定时器0 状态标志寄存器*/
#define TMR0_STFLR_CMFA_POS       (0U)
#define TMR0_STFLR_CMFA           (0x00000001UL)

/* \brief 定时器0 寄存器定义*/
typedef struct {
    volatile uint32_t CNTAR;
    volatile uint32_t CNTBR;
    volatile uint32_t CMPAR;
    volatile uint32_t CMPBR;
    volatile uint32_t BCONR;
    volatile uint32_t STFLR;
} hc32f4a0_tmr0_regs_t;

/* \brief 定时器2 寄存器定义*/
typedef struct {
    volatile uint32_t CNTAR;
    volatile uint32_t CNTBR;
    volatile uint32_t CMPAR;
    volatile uint32_t CMPBR;
    volatile uint32_t BCONR;
    volatile uint32_t ICONR;
    volatile uint32_t PCONR;
    volatile uint32_t HCONR;
    volatile uint32_t STFLR;
} hc32f4a0_tmr2_regs_t;

#define HC32F4A0_TMR0_1    ((hc32f4a0_tmr0_regs_t *)HC32F4A0_TIMER0_1_BASE)
#define HC32F4A0_TMR0_2    ((hc32f4a0_tmr0_regs_t *)HC32F4A0_TIMER0_2_BASE)

#define HC32F4A0_TMR2_1    ((hc32f4a0_tmr2_regs_t *)HC32F4A0_TIMER2_1_BASE)
#define HC32F4A0_TMR2_2    ((hc32f4a0_tmr2_regs_t *)HC32F4A0_TIMER2_2_BASE)
#define HC32F4A0_TMR2_3    ((hc32f4a0_tmr2_regs_t *)HC32F4A0_TIMER2_3_BASE)
#define HC32F4A0_TMR2_4    ((hc32f4a0_tmr2_regs_t *)HC32F4A0_TIMER2_4_BASE)
#ifdef __cplusplus
}
#endif  /* __cplusplus  */

#endif
